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A flip-flop with asynchronous inputs is a type of flip-flop that allows for immediate control over its state, regardless of the clock signal. Asynchronous inputs can override the normal operation of the flip-flop, making it change state immediately upon the assertion of the asynchronous input.
Asynchronous Inputs:
Construction:
The flip-flop includes additional input pins for asynchronous control, typically labeled as PRE (preset) and CLR (clear).
Working Principle:
When the PRE input is asserted, the flip-flop sets its output to 1 (Q=1) regardless of the clock signal.
When the CLR input is asserted, the flip-flop resets its output to 0 (Q=0) regardless of the clock signal.
Implementation:
These inputs are typically connected to additional logic gates inside the flip-flop to control the state.
Applications:
Asynchronous inputs are useful for initializing or resetting a flip-flop's state independently of the clock signal.
Active High vs Active Low Inputs:
Active High:
In active high configuration, asserting the asynchronous input is done by applying a logic high (1) voltage level to the input pin.
For example, asserting PRE in an active-high flip-flop is done by applying a logic high (1) voltage to the PRE pin.
Similarly, asserting CLR in an active-high flip-flop is done by applying a logic high (1) voltage to the CLR pin.
Active Low:
In active low configuration, asserting the asynchronous input is done by applying a logic low (0) voltage level to the input pin.
For example, asserting PRE in an active-low flip-flop is done by applying a logic low (0) voltage to the PRE pin.
Similarly, asserting CLR in an active-low flip-flop is done by applying a logic low (0) voltage to the CLR pin.
Implementation:
Active High: