TOP 50 VERILOG QUESTIONS PART -(A)

1.    What are the differences between assignments in initial and always constructs?

   Ans: While both initial and always constructs are procedural assignments, they differ in the following ways:

   

   
   

2.     What are the differences between blocking and nonblocking assignments?

   Ans: While both blocking and nonblocking assignments are procedural assignments, they differ in behaviour with respect to simulation and logic synthesis as follows:

   

3. What are the restrictions of using automatic tasks?

   Ans: The following are the restrictions of using automatic tasks:

   a. Only blocking assignments can be used on automatic variables.

   b. The variables in an automatic task shall not be referenced by procedural continuous assignments or procedural force statements. In the following code, the variable my_value in the task cannot be referenced by an assign statement.

   

4. What are the rules governing usage of a Verilog function?

   Ans: The following rules govern the usage of a Verilog function construct:

   a. A function cannot advance simulation-time, using constructs like #, @. etc.

   b. A function shall not have nonblocking assignments.

   c. A function without a range defaults to a one bit reg for the return value.

   
   

5. What are the rules governing parameter assignments?

   Ans: The rules governing the parameter assignments are as follows: The parameter override at instantiation can be done either by specifying an ordered list or by name, but not a mix of both. For example, the following is an incorrect way of specifying both width and depth.

   

   While assigning the