Module  1: RISC-V Development Environment Setup

• Install and configure Linux, Git, RISC-V GNU Toolchain, Python and Make

• Set up Verilator and GTKWave for simulation and waveform viewing

• Verify installation with a basic simulation run

Module 2: Your First RISC-V Program

• Write a simple C program and compile it with the RISC-V GCC toolchain

• Generate and inspect an ELF file

• Read generated assembly and disassembly, and explain selected instructions

Module 3: Program Analysis

• Identify entry point, .text/.data sections and instruction flow in a provided program

• Trace registers and function calls and returns

• Produce a short program-analysis report

Module 4: RISC-V Instruction Encoding & Decoding

• Decode machine instructions into type, opcode, rd, rs1, rs2, funct fields and immediates

• Cross-verify manual decoding against a disassembler

• Build a complete instruction-decoding table

Module 5: RISC-V Assembly Programming

• Write programs using arithmetic and logical instructions

• Implement loops, branches, and load/store operations

• Work with array operations and function calls

Module 6: Instruction Execution Trace

• Execute an assembly program step by step

• Analyze PC, instruction, register values and next-PC behavior

• Produce a complete execution trace deliverable

Module 7: Instruction Analysis 

• Analyze 10–15 machine instructions from a given binary

• Identify format, opcode, registers and immediate values for each

• Complete a full instruction-analysis table

Module 8: CSR Exploration

• Inspect mstatus, mtvec, mepc and mcause during processor execution

• Analyze how CSR values change across execution

• Document CSR observations and their meaning

Module 9: Exception & Trap Handling

• Generate a controlled exception during execution

• Trace mcause, mepc, mtvec, trap-handler execution and mret

• Map out the complete trap-execution flow

Module 10: Trap Analysis 

• Given a simulation trace, identify the exception raised

• Interpret mcause and determine mepc

• Explain trap entry and return behavior in a trap-analysis report

Module 11: Five-Stage Pipeline Analysis

• Analyze instruction execution through IF, ID, EX, MEM and WB stages

• Work within the CORE-V Wally pipeline context

• Produce stage-by-stage instruction analysis

Module 12: Pipeline Hazard Analysis

• Analyze RAW (read-after-write) dependencies

• Understand forwarding, stalls and dependency resolution

• Deliver a hazard analysis with timing explanation

Module 13: Waveform-Based Pipeline Debugging

• Use processor waveforms to identify pipeline stage, stalls and flushes

• Trace PC transitions and register updates through waveforms

• Produce a waveform/debug analysis report

Module 14: Pipeline Failure Analysis 

• Analyze an intentionally failing trace/waveform

• Identify hazards, stalls, forwarding issues, flushes or incorrect PC/register behavior

• Deliver a root-cause analysis

Hands-on Projects

Lab 1 — RISC-V Development Environment Setup — Set   up Linux, Git, RISC-V GNU Toolchain, Python, Make, Verilator and GTKWave,   then verify the installation with a basic simulation; skill demonstrated:   development and simulation environment setup.

Lab 2 — First RISC-V Program — Create a simple C   program, compile it with the RISC-V GCC toolchain, generate an ELF file, and   inspect the generated assembly/disassembly; skill demonstrated: C-to-RISC-V   compilation and ELF analysis.

Lab 3 — RISC-V Instruction Encoding & Decoding — Decode   machine instructions into instruction type, opcode, rd, rs1, rs2, funct   fields and immediate values, and verify results using a disassembler; skill   demonstrated: ISA-level instruction decoding.

Lab 4 — RISC-V Assembly Programming — Write   programs using arithmetic/logical instructions, loops, branches, load/store   operations, array operations and function calls; skill demonstrated: RISC-V   assembly programming.

Lab 5 — Instruction Execution Trace — Execute an   assembly program and analyze PC, instruction, register values and next-PC   behavior to produce a full execution trace; skill demonstrated:   instruction-level execution tracing.

Lab 6 — CSR Exploration — Inspect mstatus,   mtvec, mepc and mcause during processor execution and analyze how CSR values   change; skill demonstrated: privileged CSR inspection.

Lab 7 — Exception & Trap Handling — Generate   a controlled exception and trace mcause, mepc, mtvec, trap-handler execution   and mret; skill demonstrated: exception and trap-flow analysis.

Lab 8 — Five-Stage Pipeline Analysis — Analyze   instruction execution through IF, ID, EX, MEM and WB stages using the CORE-V   Wally context; skill demonstrated: pipeline stage-by-stage analysis.

Lab 9 — Pipeline Hazard Analysis — Analyze RAW   dependencies and understand forwarding, stalls and dependency resolution;   skill demonstrated: hazard detection and timing analysis.

Lab 10 — Waveform-Based Pipeline Debugging — Use   processor waveforms to identify pipeline stage, stalls, flushes, PC   transitions and register updates; tools used: CORE-V Wally, GTKWave; skill   demonstrated: waveform-based pipeline debugging.