🟩 PART A — Foundation Modules (Common to Design & Verification)

Module 1: Electronic Devices & Circuits (EDC)

• Semiconductor basics — diodes, BJTs, MOSFETs, and their characteristics

• Small-signal models, biasing, and amplifier configurations

• Digital-to-analog interface understanding for mixed-signal awareness

Module 2: Digital Electronics & Digital Design

• Boolean algebra, combinational & sequential logic

• Multiplexers, decoders, adders, comparators

• Latches, flip-flops, counters, shift registers

• FSMs (Moore/Mealy), K-map minimization

Module 3: Microprocessor Architecture

• Microprocessor architecture — registers, ALU, control unit, and buses

• Instruction cycles, addressing modes, and assembly-level understanding

• Interface with memory and I/O peripherals

Module 4: Computer Architecture

• Von Neumann vs Harvard architecture

• Pipelining, hazards, and hazard mitigation techniques

• Memory hierarchy — cache, DRAM, and virtual memory concepts

Module 5: Network Theory

• KVL, KCL, Thevenin/Norton theorems

• AC circuit analysis — impedance, phasors, frequency response

• Two-port network parameters relevant to chip I/O modelling

Module 6: Introduction to Linux

• Linux fundamentals — file system, directory structure, and permissions

• Makefile overview and build automation

• Shell commands and scripting for EDA workflows

Module 7: CMOS Fundamentals

• MOSFET (NMOS/PMOS) operation and CMOS inverter VTC

• Static, dynamic, and short-circuit power dissipation

• Layout basics and design rules overview

Module 8: Analog Design Essentials

• Op-amp configurations — inverting, non-inverting, differential

• Filters, oscillators, and feedback systems

• Analog-digital co-existence in VLSI — noise and signal integrity basics

Module 9: Puzzles, Aptitude & Placement Preparation

• Logic puzzles and reasoning problems commonly asked in VLSI interviews

• Quantitative aptitude — number theory, probability, and permutations

• Resume building and ATS-optimized formatting

• LinkedIn profile optimization for semiconductor job roles

• 100% placement support — industry connects and career counselling

✅ PART B — Verification-Specialization   Modules

Module 10: Verilog HDL — RTL & Testbench Fundamentals

• Verilog data types, operators, and modeling styles

• Synthesizable RTL for combinational and sequential circuits

• Testbench construction — stimulus, checker, and waveform analysis

Module 11: SystemVerilog HVL

• Data types, arrays, structures, and OOP (classes, inheritance, polymorphism)

• Randomization and constraint basics

• Building a basic class-based testbench

Module 12: Advanced SystemVerilog

• Advanced randomization — distributions and solve-before ordering

• Mailboxes, semaphores, events, and virtual interfaces

• Functional coverage — covergroups, coverpoints, and cross coverage

• Clocking blocks and program blocks for testbench timing

Module 13: UVM — Universal Verification Methodology

• UVM class hierarchy and component architecture

• Driver, monitor, sequencer, scoreboard, and agent construction

• Sequences and sequence items — layered sequence approach

• UVM phases, factory overrides, and configuration database (config_db)

Module 14: Assertion-Based Verification — SVA

• Immediate and concurrent assertions

• Sequences, properties, and temporal logic checks

• Binding assertions to RTL modules for protocol checking

Module 15: Code Coverage & Verification Closure

• Statement, branch, condition, toggle, and FSM coverage

• Coverage report analysis and identifying coverage holes

• Functional coverage convergence and sign-off strategy

Module 16: Verification Project — UART Protocol

• UART protocol specification — baud rate, start/stop bits, parity

• Building a complete UVM testbench for the UART DUT

• Directed and constrained-random test scenarios

• Coverage closure, bug reporting, and project documentation

Module 17: Verification Project — AMBA APB

• AMBA APB protocol — signal definitions, state machine, and transfer types

• APB master/slave UVM agent development

• Functional and protocol compliance verification

• Regression run, coverage sign-off, and mock interview

Module 18: Verification Project — AMBA AHB

• AMBA AHB protocol — burst transfers, split/retry, and arbitration

• AHB UVM environment — master, slave, and monitor agents

• Complex test scenarios — burst, error injection, and back-to-back transfers

• Full verification closure: coverage, assertions, and documentation

Projects Details: 

• UVM Testbench — FIFO/Counter DUT — Full UVM   environment: driver, monitor, scoreboard, functional coverage — demonstrates   UVM methodology

• UART Verification Project — Complete UVM-based   verification of a UART DUT with constrained-random tests and coverage closure

• AMBA APB Verification Project — APB master/slave   UVM agent, protocol compliance tests, full regression, and sign-off

• AMBA AHB Verification Project — AHB UVM   environment, burst transfer scenarios, error injection, coverage sign-off,   and mock interview