🟩 PART A — Foundation Modules (Common to Design & Verification)

Module 1: Electronic Devices & Circuits (EDC)

• Semiconductor basics — diodes, BJTs, MOSFETs, and their characteristics

• Small-signal models, biasing, and amplifier configurations

• Digital-to-analog interface understanding for mixed-signal awareness

Module 2: Digital Electronics & Digital Design

• Boolean algebra, combinational & sequential logic

• Multiplexers, decoders, adders, comparators

• Latches, flip-flops, counters, shift registers

• FSMs (Moore/Mealy), K-map minimization

Module 3: Microprocessor Architecture

• Microprocessor architecture — registers, ALU, control unit, and buses

• Instruction cycles, addressing modes, and assembly-level understanding

• Interface with memory and I/O peripherals

Module 4: Computer Architecture

• Von Neumann vs Harvard architecture

• Pipelining, hazards, and hazard mitigation techniques

• Memory hierarchy — cache, DRAM, and virtual memory concepts

Module 5: Network Theory

• KVL, KCL, Thevenin/Norton theorems

• AC circuit analysis — impedance, phasors, frequency response

• Two-port network parameters relevant to chip I/O modelling

Module 6: Introduction to Linux

• Linux fundamentals — file system, directory structure, and permissions

• Makefile overview and build automation

• Shell commands and scripting for EDA workflows

Module 7: CMOS Fundamentals

• MOSFET (NMOS/PMOS) operation and CMOS inverter VTC

• Static, dynamic, and short-circuit power dissipation

• Layout basics and design rules overview

Module 8: Analog Design Essentials

• Op-amp configurations — inverting, non-inverting, differential

• Filters, oscillators, and feedback systems

• Analog-digital co-existence in VLSI — noise and signal integrity basics

Module 9: Puzzles, Aptitude & Placement Preparation

• Logic puzzles and reasoning problems commonly asked in VLSI interviews

• Quantitative aptitude — number theory, probability, and permutations

• Resume building and ATS-optimized formatting

• LinkedIn profile optimization for semiconductor job roles

• 100% placement support — industry connects and career counselling

🔧 PART B — Design-Specialization Modules

Module 10: Verilog HDL — RTL Coding and Synthesis

• Verilog data types, operators, and modeling styles (behavioral, structural, dataflow)

• Synthesizable RTL for combinational and sequential circuits

• Testbench basics, simulation, and synthesis flow

• Gate-level netlist and synthesis report analysis

Module 11: Static Timing Analysis (STA)

• Clock concepts — setup time, hold time, clock skew, and jitter

• Timing paths — launch, capture, and timing arcs

• Setup and hold violation analysis and fixing techniques

• Slack calculation, critical path analysis, and SDC constraint basics

Module 12: Clock Domain Crossing (CDC)

• Metastability fundamentals and synchronizer design

• Single-bit and multi-bit CDC — two-flop synchronizer, handshake, FIFO-based crossing

• CDC analysis and verification methodology

Module 13: Linting

• RTL linting — what it checks and why it matters in the design flow

• Common linting rules — undriven signals, multi-driven nets, sensitivity list issues

• Running lint checks and interpreting lint reports

Module 14: Low Power Design Techniques

• Sources of power dissipation in CMOS — dynamic, static, and leakage

• Power gating, clock gating, and multi-voltage (MVD/DVFS) techniques

• UPF (Unified Power Format) concepts and low-power intent flow

Module 15: Design Project — FIFO

• Synchronous and asynchronous FIFO design in Verilog

• Full/empty flag logic, pointer arithmetic, and depth sizing

• Simulation, synthesis, and timing closure of the FIFO design

• Project documentation, review, and mock interview

Projects Overview: 

1. Combinational Circuit Design & Synthesis — ALU,   MUX, and decoder RTL design in Verilog with synthesis and netlist analysis

2. FSM-Based Controller in Verilog & VHDL — Moore/Mealy   FSM — design, simulation, and comparison across Verilog and VHDL

3. STA Lab — Timing Closure — Identify and fix   setup/hold violations on a sample design using STA tool reports

4. CDC Design Lab — Implement and verify a two-flop   synchronizer and async FIFO crossing between two clock domains

5. Low Power RTL Design Lab — Apply clock gating   and power gating to an existing RTL block; analyze power report before/after

6. FIFO Design Capstone Project — Full async FIFO   in Verilog — RTL, simulation, synthesis, timing closure, documentation, and   mock interview

7. Router 1×3 Design Project — Design a 1-input to   3-output packet router in Verilog — RTL coding, FSM-based control logic,   arbitration, simulation, synthesis, and timing closure

8. AMBA APB Design Project — RTL design of an APB   master and slave — protocol state machine, address decoding, read/write   transfers, synthesis, and STA

9. AMBA AHB Design Project — RTL design of an AHB   master, slave, and arbiter — burst transfers, HREADY control, split/retry   handling, synthesis, and full timing closure