Custom Arithmetic Logic Unit (ALU) Design Using Verilog on FPGA

An Arithmetic Logic Unit (ALU) is the core of any digital processor, responsible for carrying out mathematical and logical operations. This project focuses on the design, simulation, and FPGA-based implementation of a custom ALU using Verilog HDL. The design supports operations such as addition, subtraction, AND, OR, XOR, NOT, shift left/right, and comparison.

Using an FPGA as the implementation platform offers hardware flexibility, parallel processing, and rapid prototyping capabilities. The modular HDL-based design makes the ALU easily extendable for additional instructions, control flags (Zero, Carry, Overflow), and wider data paths.

This project provides a practical understanding of digital logic design, arithmetic operations, and FPGA synthesis, making it ideal for students, engineers, or researchers working in embedded systems, computer architecture, digital signal processing, or AI accelerators.

Project Objectives

1. Design of ALU Operations
   Implement core arithmetic operations: Add, Subtract, Increment, Decrement
   Implement logical operations: AND, OR, XOR, NOT
   Include bitwise shift and comparison functions

2. Verilog HDL Development
   Write modular and scalable Verilog code
   Implement control logic to select ALU functions based on opcode

3. Simulation and Testing
   Create testbenches for validating functionality of each operation
   Perform waveform analysis and verify correctness using simulation tools

4. FPGA Integration and Deployment
   Map the ALU design to FPGA pins and program on an FPGA board
   Use switches/buttons for input and 7-segment/LEDs for output

5. Performance Evaluation
   Analyze the timing, area, and resource usage on the target FPGA
   Verify flag outputs (Zero, Carry, Overflow) for arithmetic accuracy